
package util

import chisel3._
import chisel3.util._
import chisel3.util.experimental.loadMemoryFromFile
import firrtl.annotations.MemoryLoadFileType

class MemPort extends Bundle{
  val addr = Input(UInt(32.W))
  val data = Valid(UInt(32.W))
}
class InstrMem extends Module{
  val io = IO(new Bundle{
    val memPort = new MemPort
  })
  val addr = io.memPort.addr
  val data = io.memPort.data.bits
  val memSize = 4096
  val mem = Mem(memSize,UInt(32.W))
  loadMemoryFromFile(mem,"code.txt",hexOrBinary = MemoryLoadFileType.Hex)
  io.memPort.data.valid := {
    val ready = RegInit(false.B)
    ready := !reset.asBool()
    ready
  }
  data := {
    val data = RegInit(0.U(32.W))
    when(!reset.asBool()){
      data := mem(addr)
    }
    data
  }
}
